The present invention relates to a method and apparatus for detecting defects of a circuit pattern such as a wiring pattern on a printed wiring board or a thin film wiring pattern on a ceramic substrate, and particularly to a method and apparatus for detecting defects of pattern by compensating the expansion or contraction and the inclination of an object to be inspected.
A known method for inspecting a circuit pattern such as a wiring pattern on a printed circuit board is designed to compare a circuit pattern under test with a reference pattern derived from design data or the like, thereby detecting defects of the circuit pattern. For the comparison-based inspection, it is indispensable to align the two circuit patterns accurately. However, setting a circuit board under test to the inspection apparatus is vulnerable to the alignment error and the displacement caused by the expansion or contraction of the circuit board, and the following methods and apparatus are proposed to overcome the problem. An example described in Japanese Patent Unexamined Publication No. 61-151709 is a comparison-based inspection method which memorized a circuit pattern in a memory and reads out the circuit pattern so that the displacement is minimal. Another example described in Japanese Patent Unexamined Publication No. 2-159545 is an alignment method which modifies the evaluated dimension of a detected circuit pattern by varying the timing of pattern introduction.
The above-mentioned prior art described in the patent publication No. 61-151709 cannot recognize the displacement between the two circuit patterns if the circuit board includes an area where no circuit pattern exists, and it is incapable of aligning circuit patterns if the displacement is in excess of the preset alignment range. The resolution of alignment is limited to the accuracy of evaluation of the pattern dimension.
The above-mentioned prior art described in the patent publication No. 2-159545 is capable of aligning the circuit patterns at a resolution finer than the evaluated dimension. However, it necessitates stage pulses with a 1% accuracy of evaluated dimension for compensating a 1% displacement, for example, and it is difficult to apply the technique to the inspection of a circuit pattern with a small evaluated dimension.